Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic.
Sherif A. TawfikVolkan KursunPublished in: APCCAS (2008)
Keyphrases
- low power
- low cost
- power consumption
- logic circuits
- cmos technology
- high speed
- delay insensitive
- single chip
- nm technology
- vlsi circuits
- high power
- low power consumption
- vlsi architecture
- power reduction
- mixed signal
- computer simulation
- real time
- wireless transmission
- asynchronous circuits
- digital signal processing
- gate array