Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs.

Kizheppatt Vipin Jan Gray Nachiket Kapre

Published in: FPL (2017)

Keyphrases

low latency
high speed
real time
highly efficient
high bandwidth
high throughput
virtual machine
mobile nodes
massive scale
stream processing
routing algorithm
low cost
routing protocol
network topology
field programmable gate array
continuous query processing
routing problem
ad hoc networks
data sets