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High speed stress tolerant 1.6 V - 3.6 V low to high voltage CMOS level shift architecture in 40 nm.
Sushrant Monga
Published in:
ISCAS (2012)
Keyphrases
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high speed
high voltage
low power
cmos technology
real time
metal oxide
nm technology
operating conditions
analog vlsi
management system
normal operation
power consumption
artificial intelligence
partial discharge