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ASIC design of 7.7 Gbps multi-mode LDPC decoder for IEEE 802.11ac.
Thi Hong Tran
Yuhei Nagao
Hiroshi Ochi
Masayuki Kurosaki
Published in:
ISCIT (2014)
Keyphrases
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design methodology
hardware architecture
ldpc codes
integrated circuit
computational complexity
design tools
single chip