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Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.

Daniele LudoviciFrancisco Gilabert VillamónSimone MedardoniCrispín Gómez RequenaMaría Engracia GómezPedro LópezGeorgi Nedeltchev GaydadjievDavide Bertozzi
Published in: DATE (2009)
Keyphrases
  • design methodology
  • low cost
  • simulation environment