A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control.
Fotis PlessasEfthimios DavrazosAlexis AlexandropoulosMichael K. BirbasJohn C. KikidisPublished in: Comput. Electr. Eng. (2012)
Keyphrases
- rate control
- low power
- high speed
- power reduction
- rate distortion
- video coding
- power consumption
- visual quality
- video streaming
- rate control scheme
- bit rate
- rate control algorithm
- wavelet based image coding
- low cost
- inter frame
- video quality
- step size
- high frequency
- quality control
- multiresolution
- digital signal processing
- bitstream
- macroblock
- real time
- cost function
- digital libraries
- computational complexity
- three dimensional