Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.
Sanghyeon BaegPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
- low power
- power dissipation
- nm technology
- power consumption
- low cost
- high speed
- vlsi circuits
- single chip
- logic circuits
- digital signal processing
- high power
- image processing
- low power consumption
- power reduction
- cmos technology
- vlsi architecture
- wireless transmission
- real time
- image enhancement
- power saving
- image sensor
- mixed signal
- gate array
- contrast enhancement
- ad hoc networks
- signal processor
- ultra low power