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Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
Pascal Vivet
Christian Bernard
Eric Guthmuller
Ivan Miro Panades
Yvain Thonnart
Fabien Clermidy
Published in:
ISVLSI (2015)
Keyphrases
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power dissipation
network on chip
power consumption
low power
input output
digital signal processing
routing algorithm
finite state machines
cmos technology
interconnection networks
query processing
data access
high speed
processor core
parallel algorithm
image processing
network simulator