FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation.
Ting-Jung LinWei ZhangNiraj K. JhaPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
- low power
- reconfigurable architecture
- power consumption
- low cost
- high speed
- vlsi architecture
- cmos technology
- signal processor
- high power
- digital signal processing
- single chip
- wireless transmission
- low power consumption
- ultra low power
- image sensor
- logic circuits
- vlsi circuits
- power reduction
- systolic array
- computer vision
- efficient implementation
- gate array