13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
Jaehyeok YangHyeongjun KoKyunghoon KimHyunsu ParkJihwan ParkJi-Hyo KangJin-Youp ChaSeongjin KimYoungtaek KimMinsoo ParkGangsik LeeKeonho LeeSanghoon LeeGyunam JeonSera JeongYongsuk JooJaehoon ChaSeonwoo HwangBoram KimSang-Yeon ByeonSungkwon LeeHyeonyeol ParkJoohwan ChoJonghwan KimPublished in: ISSCC (2024)
Keyphrases
- low power
- high speed
- vlsi architecture
- low cost
- power consumption
- cmos technology
- high power
- real time
- single chip
- power dissipation
- mixed signal
- nm technology
- digital signal processing
- image sensor
- wireless transmission
- circuit design
- low power consumption
- signal processor
- power reduction
- logic circuits
- vlsi circuits
- low complexity
- design considerations
- ultra low power