An 11, 424-gate dynamic optically reconfigurable gate array VLSI.

Mao Nakajima Minoru Watanabe

Published in: FPT (2008)

Keyphrases

gate array
low power
low cost
logic circuits
signal processing
dynamic environments
genetic algorithm
power consumption
image sequences
hardware implementation
single chip
neural network
search engine
pattern recognition
high speed
reconfigurable architecture