A shift-register-based QCA memory architecture.
Baris TaskinAndy ChiuJonathan SalkindDaniel VenutoloPublished in: ACM J. Emerg. Technol. Comput. Syst. (2009)
Keyphrases
- shift register
- hardware implementation
- random number generator
- cellular automata
- management system
- high speed
- cmos technology
- real time
- memory requirements
- memory management
- processing elements
- design methodology
- memory access
- processing units
- computing power
- network architecture
- software architecture
- associative memory
- level parallelism
- neural network