Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration.
Basavaraj TalwarShailesh KulkarniBharadwaj AmruturPublished in: VLSI Design (2009)
Keyphrases
- trade off
- communication links
- transmission power
- power consumption
- network model
- high speed
- wireless sensor networks
- network latency
- link failure
- low latency
- data transfer
- early stage
- complex networks
- network structure
- integrated circuit
- network management
- resource utilization
- load balance
- distributed network
- routing protocol
- network congestion
- peer to peer
- response time
- bandwidth usage
- sensor networks