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A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology.
Mohammad Moradinezhad Maryan
Majid Amini Valashani
Seyed Javad Azhari
Published in:
Circuits Syst. Signal Process. (2021)
Keyphrases
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power dissipation
short circuit
cmos technology
logic circuits
power reduction
low power
power consumption
digital signal processing
low voltage
flip flops
low cost
high speed
power saving
finite state machines
energy efficiency
clock gating
embedded dram
silicon on insulator