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High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter.
Kota Naga Srinivasarao Batta
Indrajit Chakrabarti
Mohammad Nawaz Ahmad
Published in:
IET Circuits Devices Syst. (2015)
Keyphrases
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low power
deblocking filter
high speed
vlsi circuits
mixed signal
power consumption
low cost
cmos technology
real time
delay insensitive
frame rate
higher quality