A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation.
Norberto Pérez-PrietoManuel Delgado-RestitutoÁngel Rodríguez-VázquezPublished in: ECCTD (2017)
Keyphrases
- circuit design
- high speed
- analog vlsi
- power supply
- short circuit
- low voltage
- delay insensitive
- noise model
- random noise
- cmos technology
- noise reduction
- gaussian distribution
- low cost
- vlsi circuits
- power dissipation
- noisy data
- noise level
- power consumption
- low power
- analog circuits
- probability distribution
- transmission line
- digital circuits
- signal to noise ratio
- statistically independent
- random variables
- maximum likelihood
- chip design
- silicon on insulator