A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit.

Bongjin Kim Somnath Kundu Chris H. Kim

Published in: VLSIC (2015)

Keyphrases

clock gating
power dissipation
power consumption
flip flops
cmos technology
phase locked loop
high speed
circuit design
clock frequency
power reduction
frequency response
metal oxide semiconductor
multiple input
frequency band
digital signal processing