FPGA Design for Timing Yield Under Process Variations.
Akhilesh KumarMohab AnisPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
- design process
- information systems
- case study
- design space
- computer aided
- neural network
- verilog hdl
- single chip
- field programmable gate array
- design decisions
- design principles
- conceptual model
- development process
- software architecture
- hardware implementation
- data acquisition
- signal processing
- e learning
- hardware design
- genetic algorithm
- hardware architecture
- fpga implementation
- data sets