A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.
Yu-Huei LeeShen-Yu PengAlex Chun-Hsien WuChao-Chang ChiuYao-Yi YangMing-Hsin HuangKe-Horng ChenYing-Hsi LinShih-Wei WangChing-Yuan YehChen-Chih HuangChao-Cheng LeePublished in: VLSIC (2012)
Keyphrases
- power management
- power consumption
- low voltage
- energy consumption
- low power
- energy saving
- data center
- energy efficiency
- circuit design
- cmos technology
- delay insensitive
- mixed signal
- databases
- low cost
- text classification
- nm technology
- silicon on insulator
- high speed
- management system
- wireless sensor networks
- expert systems
- multi agent systems
- multi agent