A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.

Yu-Huei Lee Shen-Yu Peng Alex Chun-Hsien Wu Chao-Chang Chiu Yao-Yi Yang Ming-Hsin Huang Ke-Horng Chen Ying-Hsi Lin Shih-Wei Wang Ching-Yuan Yeh Chen-Chih Huang Chao-Cheng Lee

Published in: VLSIC (2012)