A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.
Yu-Huei LeeShen-Yu PengAlex Chun-Hsien WuChao-Chang ChiuYao-Yi YangMing-Hsin HuangKe-Horng ChenYing-Hsi LinShih-Wei WangChing-Yuan YehChen-Chih HuangChao-Cheng LeePublished in: VLSIC (2012)
Keyphrases