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A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS.

Pierluigi CenciMuhammed BolatkaleRobert RuttenM. GanzerliGerard LasscheKofi A. A. MakinwaLucien J. Breems
Published in: VLSI Circuits (2019)
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