Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.
Myeong-Eun HwangSeong-Ook JungKaushik RoyPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2009)
Keyphrases
- power dissipation
- cmos technology
- power consumption
- nm technology
- high speed
- low power
- chip design
- vlsi circuits
- digital signal processing
- low voltage
- analog circuits
- discrete event simulation
- simulation model
- short circuit
- mixed signal
- flip flops
- real time
- data flow
- neural network
- low cost
- single chip
- finite state machines