A parallel LSI architecture for LDPC decoder improving message-passing schedule.
Kazunori ShimizuTatsuyuki IshikawaNozomu TogawaTakeshi IkenagaSatoshi GotoPublished in: ISCAS (2006)
Keyphrases
- message passing
- ldpc codes
- shared memory
- low density parity check
- belief propagation
- distributed shared memory
- message passing interface
- distributed systems
- distributed memory
- multithreading
- parallel computing
- error correction
- scheduling problem
- decoding algorithm
- parallel programming
- sum product algorithm
- factor graphs
- vlsi architecture
- inference in graphical models
- distributed video coding
- channel coding
- parallel implementation
- markov random field
- sum product
- massively parallel