Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.

Jason Cong Yuzheng Ding

Published in: ICCAD (1993)

Keyphrases

objective function
depth map
depth information
high speed
field programmable gate array
hardware implementation
verilog hdl
regularization term
real time image processing
real time
signal processing
stereo matching
denoising
digital images
high quality
single chip
hardware architecture
inverse halftoning