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Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor.

Yifan YangGongSebastian TurullolsDaniel WooChangku HuangKing C. YenVenkatram KrishnaswamyKalon HoldbrookJinuk Luke Shin
Published in: A-SSCC (2014)
Keyphrases
  • high speed
  • clock frequency
  • real time
  • power consumption
  • low frequency
  • generation process
  • generation method
  • multi core processors
  • database
  • multiresolution
  • high frequency
  • computer architecture
  • industry standard