A low-power group-based VLD design.

Cheng-Hung Liu Bai-Jue Shieh Chen-Yi Lee

Published in: ISCAS (2) (2004)

Keyphrases

low power
single chip
low cost
power consumption
low power consumption
logic circuits
vlsi architecture
high speed
digital signal processing
design process
gate array
cmos technology
high power
power dissipation
power reduction
vlsi circuits
mixed signal
low complexity
ultra low power