A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement.
Yu-Huei LeeShen-Yu PengChao-Chang ChiuAlex Chun-Hsien WuKe-Horng ChenYing-Hsi LinShih-Wei WangTsung-Yen TsaiChen-Chih HuangChao-Cheng LeePublished in: IEEE J. Solid State Circuits (2013)