An on-chip parallel memory architecture for a stereo vision system.
Andy MottenLuc ClaesenPublished in: ICECS (2010)
Keyphrases
- level parallelism
- multithreading
- memory access
- memory bandwidth
- shared memory
- processing elements
- instruction set
- multi core processors
- memory subsystem
- parallel processing
- parallel computing
- parallel architecture
- random access memory
- distributed memory
- multi processor
- distributed processing
- analog vlsi
- vision system
- processor array
- high speed
- computational power
- parallel programming
- floating point arithmetic
- gigabit ethernet
- parallel implementation
- vlsi implementation
- processing units
- design considerations
- master slave
- compute intensive
- stereo vision
- parallel hardware
- host computer
- parallel computers
- massively parallel
- single instruction multiple data
- memory management
- real time
- power consumption
- main memory
- memory requirements
- associative memory
- cmos technology