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Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness.
Torsten Mahnke
Sebastian Panenka
Martin Embacher
Walter Stechele
Wolfgang Hoeld
Published in:
ICECS (2002)
Keyphrases
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low power
logic circuits
logic synthesis
power consumption
low cost
power dissipation
high speed
single chip
digital signal processing
vlsi circuits
vlsi architecture
low power consumption
sensor networks
image sensor
multi valued
low complexity
gate array