Bounded Depth Circuits with Weighted Symmetric Gates: Satisfiability, Lower Bounds and Compression.
Takayuki SakaiKazuhisa SetoSuguru TamakiJunichi TeruyamaPublished in: MFCS (2016)
Keyphrases
- lower bound
- logic circuits
- upper bound
- image compression
- data compression
- branch and bound algorithm
- objective function
- branch and bound
- lower and upper bounds
- high speed
- satisfiability problem
- computational complexity
- quadratic assignment problem
- propositional logic
- depth information
- compression ratio
- compression algorithm
- worst case
- compression scheme
- low power
- upper and lower bounds
- circuit design
- phase transition
- weighted graph
- sat problem
- np hard
- delay insensitive
- satisfiability testing