A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA.
Teruo JyoTadahiro KurodaHiroki IshikuroPublished in: RWS (2013)
Keyphrases
- clock gating
- power consumption
- shift register
- high speed
- power reduction
- low power
- duty cycle
- power dissipation
- random number generator
- machine learning
- inductive learning
- inductive logic programming
- electronic circuits
- circuit design
- image recovery
- rule learning
- recovery algorithm
- ultra wideband
- automatically extracting
- automatically extracted
- inductive inference
- hardware implementation
- low cost
- knowledge representation
- expert systems