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A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture.
Achim Rettberg
Mauro Cesar Zanella
Thomas Lehmann
Christophe Bobda
Published in:
IEEE International Workshop on Rapid System Prototyping (2003)
Keyphrases
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pipeline architecture
hardware implementation
low power
asynchronous communication
bit vector
shift register
query processing
run length
high bandwidth
bit vectors
genetic algorithm
computer vision
pattern recognition
efficient implementation
database
machine learning
neural network
databases