Area optimized CMOS layouts of a 50 Gb/s low power 4: 1 multiplexer.
Vibhor PareekGaurvi GoyalPublished in: VDAT (2015)
Keyphrases
- low power
- high speed
- power consumption
- low cost
- single chip
- wireless transmission
- image sensor
- cmos technology
- vlsi circuits
- high power
- low power consumption
- real time
- logic circuits
- digital signal processing
- power dissipation
- delay insensitive
- ultra low power
- mixed signal
- power reduction
- vlsi architecture
- error correction
- frame rate
- signal processor
- gate array
- video sequences