Login / Signup

Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area.

Nam Sung KimStark C. DraperShi-Ting ZhouSumeet KatariyaHamid Reza GhasemiTaejoon Park
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2012)
Keyphrases
  • low voltage
  • joint optimization
  • random access memory
  • multiple description coding
  • design considerations
  • power line
  • sparse representation
  • leakage current
  • power management
  • cmos technology
  • power consumption
  • data flow