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Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design.
Yu-Ting Chen
Jason Cong
Hui Huang
Bin Liu
Chunyue Liu
Miodrag Potkonjak
Glenn Reinman
Published in:
DATE (2012)
Keyphrases
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neural network
memory hierarchy
prefetching
memory subsystem
case study
building blocks
data access
response time
higher level
sensor networks
back end
design methodology
hybrid learning
single chip
garbage collection
database systems
embedded processors