Low power design of a word-level finite field multiplier using Reordered Normal Basis.
Parham Hosseinzadeh NaminRoberto MuscedereMajid AhmadiPublished in: ACSSC (2015)
Keyphrases
- low power
- single chip
- vlsi architecture
- low cost
- power consumption
- high speed
- low power consumption
- logic circuits
- gate array
- power dissipation
- digital signal processing
- cmos technology
- ultra low power
- mixed signal
- word level
- language independent
- pattern recognition
- information extraction
- dynamic programming
- natural language
- power reduction
- video sequences
- image processing
- computer vision