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A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop.
Yongsun Lee
Heein Yoon
Mina Kim
Jaehyouk Choi
Published in:
VLSI Circuits (2016)
Keyphrases
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domain specific
domain independent
domain knowledge
data sets
genetic algorithm
high speed
power system
robust estimation
duty cycle
neural network
image sequences
power consumption
parameter tuning
high voltage