A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA.

Ciaran Toal Sakir Sezer

Published in: AICT/SAPIR/ELETE (2005)

Keyphrases

error correction
magnetic tape
high speed
error correcting codes
error detection
xilinx virtex
data hiding
error correcting
channel coding
error control
gate array
error detection and correction
hardware architecture
low power
watermarking scheme
hardware implementation
video frames
signal processing