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Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.

Shengqi YangWayne H. WolfNarayanan VijaykrishnanYuan XieWenping Wang
Published in: VLSI Design (2005)
Keyphrases
  • power consumption
  • modeling method
  • chip design
  • high accuracy
  • power reduction
  • computationally efficient
  • high quality
  • highly accurate
  • learning algorithm
  • decision trees
  • high speed
  • power management
  • clock gating