Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.
Aleksandr ZaksZijiang YangIlya ShlyakhterFranjo IvancicSrihari CadambiMalay K. GanaiAarti GuptaPranav AsharPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2008)
Keyphrases
- model checking
- interval analysis
- temporal logic
- formal verification
- formal methods
- model checker
- temporal properties
- automated verification
- formal specification
- transition systems
- symbolic model checking
- reactive systems
- verification method
- timed automata
- software development
- software systems
- computation tree logic
- bounded model checking
- binary decision diagrams
- autocalibration
- epistemic logic
- constraint propagation
- software architecture
- artificial intelligence
- constraint programming
- camera calibration
- test cases