Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms.
Carlos Flores FajardoZhen FangRavi R. IyerGerman Fabila GarciaSeung Eun LeeLi ZhaoPublished in: DAC (2011)
Keyphrases
- cost effective
- dynamic random access memory
- low cost
- memory access
- cost effectiveness
- embedded processors
- mobile devices
- replacement policy
- embedded systems
- memory subsystem
- memory hierarchy
- virtual memory
- data access
- middleware architecture
- prefetching
- software platform
- mobile phone
- real time
- random access memory
- main memory
- data center
- multithreading
- low power
- power consumption
- hit ratio
- computing platform
- response time
- data transmission
- environmentally friendly