DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG.
Heiko AhrensRolf SchlagenhaftHelmut LangV. SrinivasanEnrico BruzzanoPublished in: ITC (2008)
Keyphrases
- level parallelism
- single chip
- analog vlsi
- vlsi implementation
- instruction set
- low cost
- compression ratio
- real time
- management system
- high speed
- image compression
- software architecture
- compression algorithm
- compression scheme
- host computer
- programmable logic
- data compression
- frequency domain
- memory access
- high density
- design methodology
- image processing