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27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS.
Yun-Shiang Shu
Liang-Ting Kuo
Tien-Yu Lo
Published in:
ISSCC (2016)
Keyphrases
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database
error rate
multiscale
low cost
circuit design