Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier.
Jinn-Shyan WangPo-Hui YangPublished in: ASP-DAC (2000)
Keyphrases
- low power
- cmos technology
- high speed
- power consumption
- low cost
- vlsi architecture
- power analysis
- signal processor
- single chip
- vlsi circuits
- high power
- logic circuits
- nm technology
- wireless transmission
- ultra low power
- gate array
- low voltage
- efficient implementation
- digital signal processing
- hardware implementation
- power dissipation
- mixed signal
- image sensor
- differential power analysis
- floating point
- countermeasures
- fixed point