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FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log Multiplier and KOM Architecture.
Satish S. Bhairannawar
R. Rathan
K. B. Raja
K. R. Venugopal
Lalit M. Patnaik
Published in:
CoRR (2014)
Keyphrases
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error free
hardware implementation
image processing
floating point
signal processing
computer vision
edge detection
multiscale
multiresolution
error prone