Genetic Algorithm based Approach for Low Power Combinational Circuit Testing.
Santanu ChattopadhyayNaveen ChoudharyPublished in: VLSI Design (2003)
Keyphrases
- low power
- logic circuits
- genetic algorithm
- high speed
- power consumption
- low cost
- gate array
- cmos technology
- vlsi circuits
- high power
- single chip
- wireless transmission
- power dissipation
- power reduction
- delay insensitive
- digital signal processing
- mixed signal
- real time
- vlsi architecture
- low power consumption
- image sensor
- nm technology