Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution.
Jeff Jun ZhangKanad BasuSiddharth GargPublished in: IEEE Des. Test (2019)
Keyphrases
- message passing
- fault tolerant
- systolic array
- distributed systems
- neural network
- data flow
- fault tolerance
- reconfigurable architecture
- parallel architecture
- load balancing
- pattern recognition
- state machine
- high availability
- parallel processing
- fault diagnosis
- fuzzy logic
- safety critical
- high assurance
- computer vision