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A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs.

Kanad ChakrabortyPinaki Mazumder
Published in: ED&TC (1997)
Keyphrases
  • co occurrence
  • general purpose
  • low cost
  • n gram
  • parallel processing
  • neural network
  • object boundaries
  • levels of abstraction
  • parallel implementation
  • word level
  • processor array