Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation.
In-Cheol ParkSe-Hyeon KangPublished in: ISCAS (6) (2005)
Keyphrases
- scheduling algorithm
- parallel architecture
- ldpc codes
- low density parity check
- shared memory
- message passing
- response time
- distributed source coding
- turbo codes
- parallel processing
- decoding algorithm
- systolic array
- hardware implementation
- distributed video coding
- scheduling strategy
- error correction
- high level synthesis
- distributed memory
- low complexity
- channel coding
- error concealment
- parallel implementation
- graphical models
- error resilience
- compressive sensing
- distributed systems