AES crypto chip utilizing high-speed parallel pipelined architecture.
Deen KotturiSeong-Moo YooJohn BlizzardPublished in: ISCAS (5) (2005)
Keyphrases
- high speed
- pipelined architecture
- hardware implementation
- low power
- advanced encryption standard
- field programmable gate array
- low power consumption
- real time
- neural network
- machine learning
- parallel processing
- parallel computing
- fault model
- image processing
- access control
- efficient implementation
- parallel implementation
- encryption algorithms