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Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs.
Koki Abe
Masataka Ishihara
Yusuke Hatakenaka
Kazuhiro Umetani
Eiji Hiraki
Published in:
ISIE (2021)
Keyphrases
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high level synthesis
user interface
logic circuits
electronic circuits
design process
tunnel diode
data sets
evolutionary algorithm
knowledge based systems
computer aided
design principles
cost effectiveness